The invention relates to data coding, and particularly to data coding for achieving bit and byte synchronization using a single data field.
Bit synchronization refers to the synchronization of a clock for receiving or reading incoming data with the data being received or read. Normally, bit synchronization is achieved when a field of, say, 1s (ones), is written as the data is stored (or transmitted) in a partial-response, maximum-likelihood sequence (“PRML”) channel, and it is sampled using an acquisition loop. In a PRML channel, byte synchronization refers to a field with a data pattern in the data that marks the first bit of a symbol. For byte synchronization, this field is followed by a pattern that, when recognized, determines the start of data. Thus, data can be sampled and the information retrieved in the usual form.
As pointed out in U.S. Pat. No. 6,089,749, the conventional byte synchronization approach has the disadvantage of a long synchronization pattern, with a significant possibility of synchronization failure. The '749 patent proposes a byte synchronization scheme using a byte synchronization pattern between 16 and 18 bits in length.
Our purpose is to unify both the bit synchronization and byte synchronization fields into a single field and achieve bit and byte synchronization simultaneously using the single field (“bit-byte synchronization”). The idea is that the new field is short, allowing for significant savings in magnetic disk real estate. Alternatively, the new field can be used in a hybrid way. In order to combat events like thermal asperity (TA) that wipes out a whole synchronization field, a dual synchronization architecture has been proposed: the bit-byte synchronization field is repeated twice, so if the first bit-byte synchronization field is wiped out, then the system relies on the second one to achieve synchronization. One of the problems associated with TA is loss of both bit and byte synchronization. For that reason, it would be useful to have a synchronization field that recovers bit and byte synchronization simultaneously. Such a capability is disclosed in the following specification.